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This team project involved designing and building our own processor using the Y86-64 instruction set architecture (ISA) to gain a deeper understanding of the inner workings of microprocessors, particularly how they execute programs. We used Logisim-evolution, a digital logic simulator, to implement and visualize the processor’s operations. Our design followed the Von Neumann architecture, which is characterized by the use of a single memory space for both instructions and data, allowing for streamlined data and instruction handling. The project was divided into six key stages: Fetch - processor retrieves the next instruction from the instruction memory based on the Program Counter, Decode - The instruction is then decoded to determine what operations are required. This involves reading from the register file, Execute - The ALU performs the specified operation, Memory - Some instructions require interaction with the data memory. In this stage, the processor may read data from or write data to the RAM, Write Back - The results of the ALU operations or memory fetches are written back to the register file, and PC Update - The Program Counter is updated to point to the next instruction. We began by working with a predefined set of instructions known as the Instruction Set Architecture (ISA). The processor first fetches instructions from the "instruction memory" sequentially. Each instruction is then decoded and executed. Some instructions require the processor to fetch data from the "data memory" and write results back to the data memory during execution. We implemented each stage independently, ensuring proper functionality before integrating them. The stages were synchronized using clock cycles, which was challenging, as certain stages required precise timing and delays to ensure that outputs were ready for subsequent stages. Finally, we tested our processor with three different assembly programs that we wrote: a Palindrome Checker, a Bubble Sort algorithm, and a program to sum the first 100 numbers. These tests covered a range of instruction types to help us validate the accuracy and efficiency of our processor design.